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The following R&D paper is a major part of the research into the Physics of Thought. ©Copyright 1978 - 2002 Advanced Research Consultants, Inc. P1-3, P4-6, P7-10, P11-16, P17-20
Consider the logic equations of the output bi-stable devices. The SET (set output to “1”) equation of first output bit is merely the start coordinate (SC) and (logical AND) the Core (C) selected by the start coordinate. Equation 5: S1
= SC1·C1 + SC2·C2 + SC3·C3
+ SC4·C4 + SC5·C5 + SC6·C6 + SC7·C7
+ SC8·C8 + SC10·C10 + SC11·C11 + SC12·C12 + SC13·C13 + SC14·C14 + SC15·C15 + SC16·C16 Reading from the associated figures, we have the SET (set output to “1”) equations for the remaining three output bi-stable devices (S2, S3 and S4) in our output register. Equation
6: S2 = SC1·(V1·C2 +
V2·C16 + V3·C14 + V4·C5
+ V5·C6 + V6·C12
+ V7·C5 + V8·C16) + SC2·(V1·C3
+ V2·C1 + V3·C15
+ V4·C6 + V5·C12
+ V6·C8 + V7·C9
+ V8·C5 ) + SC3·(V1·C4 +
V2·C2 + V3·C16
+ V4·C7 + V5·C8
+ V6·C4 + V7·C13 + V8·C6
) + SC4·(V1·C5 +
V2·C3 + V3·C13
+ V4·C8 + V5·C3
+ V6·C13 + V7·C14
+ V8·C7 ) + SC5·(V1·C6 +
V2·C4 + V3·C1
+ V4·C9 + V5·C10 + V6·C16
+ V7·C2 + V8·C1
) + SC6·(V1·C7 +
V2·C5 + V3·C2
+ V4·C10 + V5·C11
+ V6·C1 + V7·C3
+ V8·C9 ) + SC7·(V1·C8 +
V2·C6 + V3·C3
+ V4·C11 + V5·C12
+ V6·C2 + V7·C4
+ V8·C10) + SC8·(V1·C9 +
V2·C7 + V3·C4
+ V4·C12 + V5·C2
+ V6·C3 + V7·C15 + V8·C11) + SC9·(V1·C10+
V2·C8 + V3·C5
+ V4·C13 + V5·C14
+ V6·C15 + V7·C6 + V8·C2 ) + SC10·(V1·C11 +
V2·C9 + V3·C6
+ V4·C14 + V5·C15 + V6·C5 + V7·C7 + V8·C13) + SC11·(V1·C12 +
V2·C10 + V3·C7 + V4·C15
+ V5·C16 + V6·C6 + V7·C8 + V8·C14) + SC12·(V1·C13 +
V2·C11 + V3·C8 + V4·C16
+ V5·C1 + V6·C7
+ V7·C16 + V8·C15) + SC13·(V1·C14 +
V2·C12 + V3·C9 + V4·C4 + V5·C4 + V6·C14 + V7·C10
+ V8·C3 ) + SC14·(V1·C15 +
V2·C13 + V3·C10 + V4·C1 + V5·C13 + V6·C9
+ V7·C11 + V8·C4
) + SC15·(V1·C16 +
V2·C14 + V3·C11 + V4·C2 + V5·C9 + V6·C10 + V7·C12
+ V8·C8 ) + SC16·(V1·C1 + V2·C15 + V3·C12
+ V4·C3 + V5·C5
+ V6·C11 + V7·C1 + V8·C12) Equation
7: S3 = SC1·(V1·C3 +
V2·C15 + V3·C10 + V4·C9
+ V5·C11 + V6·C7 + V7·C2 + V8·C12) + SC2·(V1·C4 +
V2·C16 + V3·C11 + V4·C10
+ V5·C12 + V6·C3 + V7·C6 + V8·C1 ) + SC3·(V1·C5 +
V2·C1 + V3·C12
+ V4·C11 + V5·C2 + V6·C13 + V7·C10
+ V8·C9 ) + SC4·(V1·C6 +
V2·C2 + V3·C9
+ V4·C12 + V5·C8
+ V6·C14 + V7·C11
+ V8·C10) + SC5·(V1·C7 +
V2·C3 + V3·C14
+ V4·C13 + V5·C15 + V6·C11
+ V7·C9 + V8·C16) + SC6·(V1·C8 +
V2·C4 + V3·C15
+ V4·C14 + V5·C16 + V6·C12
+ V7·C13 + V8·C2 ) + SC7·(V1·C9 +
V2·C5 + V3·C16
+ V4·C15 + V5·C1 + V6·C8 + V7·C14 + V8·C13) + SC8·(V1·C10+
V2·C6 + V3·C13
+ V4·C16 + V5·C7 + V6·C4 + V7·C12 + V8·C14) + SC9·(V1·C11+
V2·C7 + V3·C1
+ V4·C4 + V5·C13 + V6·C10
+ V7·C3 + V8·C5
) + SC10·(V1·C12 +
V2·C8 + V3·C2
+ V4·C1 + V5·C9 + V6·C16 + V7·C4
+ V8·C3 ) + SC11·(V1·C13 +
V2·C9 + V3·C3
+ V4·C2 + V5·C5 + V6·C1 + V7·C15 + V8·C4
) + SC12·(V1·C14 +
V2·C10 + V3·C4 + V4·C3 + V5·C6 + V6·C2 + V7·C1 + V8·C8 ) + SC13·(V1·C15 +
V2·C11 + V3·C5
+ V4·C8 +
V5·C3 + V6·C9
+ V7·C7 + V8·C6 ) + SC14·(V1·C16 +
V2·C12 + V3·C6
+ V4·C5 +
V5·C4 + V6·C15
+ V7·C8 + V8·C7
) + SC15·(V1·C1 + V2·C13 + V3·C7 + V4·C6 + V5·C14 + V6·C5
+ V7·C16 + V8·C11) + SC16·(V1·C2 + V2·C14 + V3·C8 + V4·C7 + V5·C10 + V6·C6
+ V7·C5 + V8·C15) ©Copyright 2002 Advanced Research Consultants, Inc. Page 11 of 20 pages Equation
8: S4 = SC1·(V1·C4 + V2·C14
+ V3·C6 + V4·C13 + V5·C16
+ V6·C2 +
V7·C9 +
V8·C15)
+ SC2·(V1·C5 + V2·C15 + V3·C7
+ V4·C14 +
V5·C1 +
V6·C4 +
V7·C3 +
V8·C16)
+ SC3·(V1·C6 + V2·C16 + V3·C8
+ V4·C15 +
V5·C7 +
V6·C14 + V7·C7 +
V8·C2 )
+ SC4·(V1·C7 + V2·C1 +
V3·C5
+ V4·C16 +
V5·C2 +
V6·C9 +
V7·C8 +
V8·C13)
+ SC5·(V1·C8 + V2·C2 +
V3·C10 + V4·C4
+ V5·C9 +
V6·C6 +
V7·C6 +
V8·C12)
+ SC6·(V1·C9 + V2·C3 +
V3·C11 + V4·C1
+ V5·C5 +
V6·C7 +
V7·C10 + V8·C5 )
+ SC7·(V1·C10+ V2·C4 +
V3·C12 + V4·C2
+ V5·C6 +
V6·C3 +
V7·C11 + V8·C3 )
+ SC8·(V1·C11+ V2·C5 +
V3·C9 +
V4·C3
+ V5·C12 + V6·C13 + V7·C16
+ V8·C4 )
+ SC9·(V1·C12+ V2·C6 +
V3·C14 + V4·C8
+ V5·C4 +
V6·C5 +
V7·C13 + V8·C1 )
+ SC10·(V1·C13 + V2·C7 +
V3·C15 + V4·C5 +
V5·C14 + V6·C11 + V7·C14 +
V8·C6 )
+ SC11·(V1·C14 + V2·C8 +
V3·C16 + V4·C6 +
V5·C10 + V6·C12 + V7·C12 +
V8·C7 )
+ SC12·(V1·C15 + V2·C9 +
V3·C13 + V4·C7 +
V5·C11 + V6·C8 +
V7·C5
+ V8·C11)
+ SC13·(V1·C16 + V2·C10 +
V3·C1
+ V4·C12 + V5·C8 +
V6·C15 + V7·C4
+ V8·C9 )
+ SC14·(V1·C1
+ V2·C11 + V3·C2
+ V4·C9 +
V5·C3 +
V6·C10 + V7·C15 + V8·C10)
+ SC15·(V1·C2
+ V2·C12 + V3·C3
+ V4·C10 + V5·C13 + V6·C16
+ V7·C1
+ V8·C14)
+
SC16·(V1·C3
+V2·C13 + V3·C4
+ V4·C11 + V5·C15 + V6·C1
+
V7·C2
+ V8·C8 ) · Reducing
these Boolean equations using the fact that all Cij’s are fixed at 1 or 0
and the Boolean relationships: X·1=X, X·0=0. As
many of you saw at the outset, all terms containing cores equal to “0” vanish
and all terms with cores equal to “1” remain without the core. S1 becomes merely the start coordinates
of cores that are “1”. Equation
9: S1
= SC5 + SC8 + SC9 + SC11 + SC13
+ SC14 + SC15 + SC16 The
other SET equations become: Equation
10: S2
= SC1·(V2 + V3 + V4 + V7 + V8) + SC2·(V3 + V6 +
V7 + V8) + SC3·(V3 + V5 +
V7) + SC4·(V1 + V3 +
V4 + V6 + V7) + SC5·(V4 + V6) + SC6·(V2 + V5 +
V8) + SC7·(V1 + V4) + SC8·(V1 + V7 +
V8) + SC9·(V2 + V3 +
V4 + V5 + V6) + SC10·(V1 + V2 +
V4 + V5 + V6 + V8) + SC11·(V4 + V5
+ V7 + V8) + SC12·(V1 + V2
+ V3 + V4 + V7 + V8) + SC13·(V1 + V3
+ V6) + SC14·(V1 + V2
+ V5 + V6 + V7) + SC15·(V1 + V2
+ V3 + V5 + V8) + SC16·(V2 + V5
+ V6) ©Copyright 2002 Advanced Research Consultants, Inc. Page 12 of 20 pages Equation
11: S3
= SC1·(V2 + V4 + V5) + SC2·(V2 + V3) + SC3·(V1 + V4 +
V6 + V8) + SC4·(V3 + V5 +
V6 + V7) + SC5·(V3 + V4 +
V5 + V6 + V7 + V8) + SC6·(V1 + V3 +
V4 + V5 + V7) + SC7·(V1 + V2 +
V3 + V4 + V6 + V7 + V8) + SC8·(V3 + V4 +
V8) + SC9·(V1 + V5 +
V8) + SC10·(V2 + V5 +
V6) + SC11·(V1 + V2
+ V5 + V7) + SC12·(V1 + V8) + SC13·(V1 + V2
+ V3 + V4 + V6) + SC14·(V1 + V4
+ V6 + V7) + SC15·(V2 + V5
+ V6 + V7 + V8) + SC16·(V2 + V3 +
V8) Equation
12: S4
= SC1·(V2 + V4 + V5 + V7 + V8) + SC2·(V1 + V2 +
V4 + V8) + SC3·(V2 + V3 +
V4 + V6) + SC4·(V3 + V4 + V6 + V7 +
V8) + SC5·(V1 + V5) + SC6·(V1 + V3 +
V5 + V8) + SC7·(V7) + SC8·(V1 + V2 +
V3 + V6 + V7) + SC9·(V3 + V4 +
V6 + V7) + SC10·(V1 + V3 +
V4 + V5 + V6 + V7) + SC11·(V1 + V2 +
V3) + SC12·(V1 + V2 +
V3 + V5 + V6 + V7 + V8) + SC13·(V1 + V5 +
V6 + V8) + SC14·(V2 + V4 +
V7) + SC15·(V5 + V6 +
V8) + SC16·(V2 + V4 +
V5 + V8) POOF!
The CORE is gone! Only the logic circuits
remain to output 110 (4-bit) words!!?? Where
are those 110 words stored? IN THE LOGIC / CIRCUIT? Logic
equations 9 through 12 provide a view of the input seen by each of the four output devices
in terms of each Start Coordinate and associated Read Vectors. Another view appears when we reduce equations 10,
11 and 12 by (a) expand, (b) rearrange and (c) reduce. ©Copyright 2002 Advanced Research Consultants, Inc. Page 13 of 20 pages 10a S2
= V2·SC1 + V3·SC1 + V4·SC1
+ V7·SC1 + V8·SC1 + V3·SC2 + V6·SC2
+ V7·SC2 + V8·SC2 + V3·SC3 + V5·SC3
+ V7·SC3 + V1·SC4 + V3·SC4
+ V4·SC4 + V6·SC4 + V7·SC4 + V4·SC5 + V6·SC5 + V2·SC6 + V5·SC6
+ V8·SC6 + V1·SC7 + V4·SC7 + V1·SC8 + V7·SC8
+ V8·SC8 + V2·SC9 + V3·SC9
+ V4·SC9 + V5·SC9 + V6·SC9 + V1·SC10 + V2·SC10
+ V4·SC10 + V5·SC10 + V6·SC10
+ V8·SC10 + V4·SC11 + V5·SC11
+ V7·SC11 + V8·SC11 + V1·SC12 + V2·SC12
+ V3·SC12 + V4·SC12 + V7·SC12
+ V8·SC12 + V1·SC13 + V3·SC13
+ V6·SC13 + V1·SC14 + V2·SC14
+ V5·SC14 + V6·SC14 + V7·SC14 + V1·SC15 + V2·SC15
+ V3·SC15 + V5·SC15 + V8·SC15 + V2·SC16 + V5·SC16
+ V6·SC16 10b S2
= V1·SC4 + V1·SC7 + V1·SC8
+ V1·SC10 + V1·SC12 + V1·SC13
+ V1·SC14 + V1·SC15 + V2·SC1 + V2·SC6
+ V2·SC9 + V2·SC10 + V2·SC12
+ V2·SC14 + V2·SC15 + V2·SC16
+ V3·SC1 + V3·SC2
+ V3·SC3 + V3·SC4 + V3·SC9 + V3·SC12 + V3·SC13
+ V3·SC15 + V4·SC1 + V4·SC4
+ V4·SC5 + V4·SC7 + V4·SC9 + V4·SC10 + V4·SC11
+ V4·SC12 + V5·SC3 + V5·SC6
+ V5·SC9 + V5·SC10 + V5·SC11
+ V5·SC14 + V5·SC15 + V5·SC16 + V6·SC2 + V6·SC4
+ V6·SC5 + V6·SC9 + V6·SC10 + V6·SC13
+ V6·SC14 + V6·SC16 + V7·SC1 + V7·SC2
+ V7·SC3 + V7·SC4 + V7·SC8 + V7·SC11 + V7·SC12
+ V7·SC14 + V8·SC1 + V8·SC2
+ V8·SC6 + V8·SC8 + V8·SC10 + V8·SC11
+ V8·SC12 + V8·SC15
10c S2
= V1·(SC4 + SC7 + SC8 + SC10 +
SC12 + SC13 + SC14 + SC15) + V2·(SC1 + SC6 +
SC9 + SC10 + SC12 + SC14 + SC15 +
SC16) + V3·(SC1 + SC2 +
SC3 + SC4 + SC9 + SC12 + SC13 + SC15)
+ V4·(SC1 + SC4 +
SC5 + SC7 + SC9 + SC10 + SC11 + SC12) + V5·(SC3 + SC6 +
SC9 + SC10 + SC11 + SC14 + SC15 +
SC16) + V6·(SC2 + SC4 +
SC5 + SC9 + SC10
+ SC13 + SC14 + SC16) + V7·(SC1 + SC2 +
SC3 + SC4 + SC8 + SC11 + SC12 + SC14) + V8·(SC1 + SC2 + SC6 + SC8 + ©Copyright 2002 Advanced Research Consultants, Inc. Page 14 of 20 pages 11a S3
= V2·SC1 + V4·SC1 + V5·SC1 + V2·SC2 + V3·SC2 + V1·SC3 + V4·SC3
+ V6·SC3 + V8·SC3 + V3·SC4 + V5·SC4
+ V6·SC4 + V7·SC4 + V3·SC5 + V4·SC5
+ V5·SC5 + V6·SC5 + V7·SC5
+ V8·SC5 + V1·SC6 + V3·SC6
+ V4·SC6 + V5·SC6 + V7·SC6) + V1·SC7 + V2·SC7
+ V3·SC7 + V4·SC7 + V6·SC7
+ V7·SC7 + V8·SC7 + V3·SC8 + V4·SC8
+ V8·SC8 + V1·SC9 + V5·SC9
+ V8·SC9 + V2·SC10 + V5·SC10
+ V6·SC10 + V1·SC11 + V2·SC11
+ V5·SC11 + V7·SC11 + V1·SC12 + V8·SC12 + V1·SC13 + V2·SC13
+ V3·SC13 + V4·SC13 + V6·SC13 + V1·SC14 + V4·SC14
+ V6·SC14 + V7·SC14 + V2·SC15 + V5·SC15
+ V6·SC15 + V7·SC15 + V8·SC15 + V2·SC16 + V3·SC16
+ V8·SC16 11b S3
= V1·SC3+ V1·SC6+ V1·SC7+
V1·SC9+ V1·SC11+ V1·SC12+
V1·SC13+ V1·SC14 + V2·SC1+ V2·SC2+
V2·SC7+ V2·SC10+ V2·SC11
+ V2·SC13+ V2·SC15+ V2·SC16
+ V3·SC2+ V3·SC4+
V3·SC5+ V3·SC6+ V3·SC7+
V3·SC8 + V3·SC13+ V3·SC16 + V4·SC1+ V4·SC3+
V4·SC5+ V4·SC6+ V4·SC7+
V4·SC8+ V4·SC13+ V4·SC14
+ V5·SC1+ V5·SC4+
V5·SC5+ V5·SC6+ V5·SC9+
V5·SC10+ V5·SC11+ V5·SC15 + V6·SC3+ V6·SC4
+ V6·SC5+ V6·SC7+ V6·SC10+
V6·SC13+ V6·SC14+ V6·SC15
+ V7·SC4+ V7·SC5+
V7·SC6+ V7·SC7+ V7·SC11+
V7·SC14+ V7·SC15 + V8·SC3+ V8·SC5+
V8·SC7+ V8·SC8+ V8·SC9+
V8·SC12+ V8·SC15+ V8·SC16 11c S3
= V1·(SC3 + SC6 + SC7 + SC9 + SC11 + SC12 + SC13
+ SC14 ) + V2·(SC1 + SC2 +
SC7 + SC10 + SC11 + SC13 + SC15 +
SC16) + V3·(SC2 + SC4 +
SC5 + SC6 + SC7 +
SC8 + SC13 + SC16) + V4·(SC1 + SC3 +
SC5 + SC6 + SC7 +
SC8 + SC13 + SC14
) + V5·(SC1 + SC4 +
SC5 + SC6 + SC9 +
SC10 + SC11 + SC15) + V6·(SC3 + SC4
+ SC5 + SC7 + SC10 + SC13 + SC14 +
SC15) + V7·(SC4 + SC5 +
SC6 + SC7 + SC11 + SC14 + SC15 ) + V8·(SC3 + SC5 +
SC7 + SC8 + SC9 + SC12 + SC15 + SC16) 12a
S4 = V2·SC1 + V4·SC1
+ V5·SC1 + V7·SC1 + V8·SC1 + V1·SC2 + V2·SC2
+ V4·SC2 + V8·SC2 + V2·SC3 + V3·SC3
+ V4·SC3 + V6·SC3 + V3·SC4 + V4·SC4 + V6·SC4
+ V7·SC4 + V8·SC4 + V1·SC5 + V5·SC5 + V1·SC6 + V3·SC6
+ V5·SC6 + V8·SC6 + V7·SC7 + V1·SC8 + V2·SC8
+ V3·SC8 + V6·SC8 + V7·SC8 + V3·SC9 + V4·SC9
+ V6·SC9 + V7·SC9 + V1·SC10 + V3·SC10
+ V4·SC10 + V5·SC10 + V6·SC10
+ V7·SC10 + V1·SC11 + V2·SC11
+ V3·SC11 + V1·SC12 + V2·SC12
+ V3·SC12 + V5·SC12 + V6·SC12
+ V7·SC12 + V8·SC12 + V1·SC13 + V5·SC13
+ V6·SC13 + V8·SC13 + V2·SC14 + V4·SC14
+ V7·SC14 + V5·SC15 + V6·SC15
+ V8·SC15 + V2·SC16 + V4·SC16
+ V5·SC16 + V8·SC16 ©Copyright 2002 Advanced Research Consultants, Inc. Page 15 of 20 pages 12b S4
= V1·SC2+ V1·SC5+ V1·SC6+
V1·SC8+ V1·SC10+ V1·SC11+
V1·SC12+ V1·SC13
+
V2·SC1+ V2·SC2+ V2·SC3+
V2·SC8+ V2·SC11+ V2·SC12+
V2·SC14+ V2·SC16 + V3·SC3+ V3·SC6+
V3·SC8+ V3·SC9+ V3·SC10+
V3·SC11+ V3·SC12
+
V4·SC1+ V4·SC2 + V4·SC3+
V4·SC4+ V4·SC9+ V4·SC10+
V4·SC14+ V4·SC16 + V5·SC1+ V5·SC5+
V5·SC6+ V5·SC10+ V5·SC12+
V5·SC13 + V5·SC15+ V5·SC16 + V6·SC3+ V6·SC8+
V6·SC9+ V6·SC10+ V6·SC12+
V6·SC13+ V6·SC15 + V7·SC1+ V7·SC4+
V7·SC7+ V7·SC8+ V7·SC9+
V7·SC10+ V7·SC12+ V7·SC14 + V8·SC1+ V8·SC2+
V8·SC4+ V8·SC6+ V8·SC12+
V8·SC13+ V8·SC15+ V8·SC16 12c S4
= V1·(SC2 + SC5 + SC6 + SC8 +
SC10 + SC11 + SC12 + SC13) + V2·(SC1 + SC2 +
SC3 + SC8 + SC11 +
SC12 + SC14 + SC16) + V3·(SC3 + SC6 +
SC8 + SC9 + SC10 +
SC11 + SC12)
+
V4·(SC1 + SC2 + SC3 + SC4 + SC9
+ SC10 + SC14 + SC16) + V5·(SC1 + SC5 +
SC6 + SC10 + SC12 + SC13 + SC15 +
SC16) + V6·(SC3 + SC8 +
SC9 + SC10 + SC12 + SC13 + SC15) + V7·(SC1 + SC4 +
SC7 + SC8 + SC9 + SC10 + SC12 + SC14) + V8·(SC1 + SC2 +
SC4 + SC6 + SC12 +
SC13 + SC15 + SC16) These
logic equations can be burned into circuits which will produce, and output, the 4-bit
words called out in tables 1 though 8. One
way of looking at this is that the data (110: 4-bit words) is stored in the SET (set
output to “1”) logic circuits. However
when we move to larger words, stored using more sophisticated storage techniques, in as
many dimensions as we choose, this picture of the data stored in the logic breaks down. Consider information stored in the human brain. We have 1010 neurons (delay elements). We store in excess of 1060 bits of
information in 30 years of living according to Von Neuman (reference). Another way of looking says that the data is in “Information Space” and the logic circuits taken together is the real world transform (T prime of equation 3 chapter 1 of The Physics of Thought - reference) containing the addresses of the data. To see how this can be done, consider the following expansion direction. The size of the address: 4 bits for the Start Coordinate and 3 bits for the Read Vector. The total is a 7-bit address of a 4-bit word. If the word size is increased we find that the address size does not increase at the same rate. Suppose
we now move to a cube (x,y,z) 256 bits on an edge. AND suppose we can find a distribution of
“1”s and “0”s such that EVERY 256-bit word can be found in every read
direction as demonstrated with the 110 4-bit words discussed above. Considering addressing schemes of the type we have
been exploring, we find that it requires 8 bits to specify a “Start Coordinate”
in each direction in our cube: 28=256. Therefore
24 (3 axes x 8) bits are used in the “Start Coordinate”. ©Copyright 2002 Advanced Research Consultants, Inc. Page 16 of 20 pages
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