ICM4

Consider the logic equations of the output bi-stable devices.

The SET (set output to “1”) equation of first output bit is merely the start coordinate (SC) and (logical AND) the Core (C) selected by the start coordinate.

Equation 5:

S₁= SC₁·C₁+ SC₂·C₂ + SC₃·C₃ + SC₄·C₄ + SC₅·C₅ + SC₆·C₆ + SC₇·C₇ + SC₈·C₈ + SC₉·C₉

+ SC₁₀·C₁₀ + SC₁₁·C₁₁ + SC₁₂·C₁₂ + SC₁₃·C₁₃ + SC₁₄·C₁₄ + SC₁₅·C₁₅+ SC₁₆·C₁₆

Reading from the associated figures, we have the SET (set output to “1”) equations for the remaining three output bi-stable devices (S₂, S₃ and S₄) in our output register.

Equation 6:

S₂= SC₁·(V₁·C₂+ V₂·C₁₆ + V₃·C₁₄ + V₄·C₅ + V₅·C₆ + V₆·C₁₂ + V₇·C₅ + V₈·C₁₆)

+ SC₂·(V₁·C₃+ V₂·C₁ + V₃·C₁₅ + V₄·C₆ + V₅·C₁₂ + V₆·C₈ + V₇·C₉ + V₈·C₅)

+ SC₃·(V₁·C₄+ V₂·C₂ + V₃·C₁₆ + V₄·C₇ + V₅·C₈ + V₆·C₄ + V₇·C₁₃ + V₈·C₆)

+ SC₄·(V₁·C₅+ V₂·C₃ + V₃·C₁₃ + V₄·C₈ + V₅·C₃ + V₆·C₁₃ + V₇·C₁₄ + V₈·C₇)

+ SC₅·(V₁·C₆+ V₂·C₄ + V₃·C₁ + V₄·C₉ + V₅·C₁₀ + V₆·C₁₆ + V₇·C₂ + V₈·C₁)

+ SC₆·(V₁·C₇+ V₂·C₅ + V₃·C₂ + V₄·C₁₀ + V₅·C₁₁ + V₆·C₁ + V₇·C₃ + V₈·C₉)

+ SC₇·(V₁·C₈+ V₂·C₆ + V₃·C₃ + V₄·C₁₁ + V₅·C₁₂ + V₆·C₂ + V₇·C₄ + V₈·C₁₀)

+ SC₈·(V₁·C₉+ V₂·C₇ + V₃·C₄ + V₄·C₁₂ + V₅·C₂ + V₆·C₃ + V₇·C₁₅ + V₈·C₁₁)

+ SC₉·(V₁·C₁₀+ V₂·C₈ + V₃·C₅ + V₄·C₁₃ + V₅·C₁₄ + V₆·C₁₅ + V₇·C₆ + V₈·C₂)

+ SC₁₀·(V₁·C₁₁+ V₂·C₉ + V₃·C₆ + V₄·C₁₄ + V₅·C₁₅ + V₆·C₅ + V₇·C₇ + V₈·C₁₃)

+ SC₁₁·(V₁·C₁₂+ V₂·C₁₀ + V₃·C₇ + V₄·C₁₅ + V₅·C₁₆ + V₆·C₆ + V₇·C₈+ V₈·C₁₄)

+ SC₁₂·(V₁·C₁₃+ V₂·C₁₁ + V₃·C₈ + V₄·C₁₆ + V₅·C₁ + V₆·C₇ + V₇·C₁₆+ V₈·C₁₅)

+ SC₁₃·(V₁·C₁₄+ V₂·C₁₂ + V₃·C₉ + V₄·C₄ + V₅·C₄ + V₆·C₁₄ + V₇·C₁₀+ V₈·C₃)

+ SC₁₄·(V₁·C₁₅+ V₂·C₁₃ + V₃·C₁₀+ V₄·C₁ + V₅·C₁₃ + V₆·C₉ + V₇·C₁₁+ V₈·C₄)

+ SC₁₅·(V₁·C₁₆+ V₂·C₁₄ + V₃·C₁₁+ V₄·C₂ + V₅·C₉ + V₆·C₁₀ + V₇·C₁₂+ V₈·C₈)

+ SC₁₆·(V₁·C₁+ V₂·C₁₅ + V₃·C₁₂+ V₄·C₃ + V₅·C₅ + V₆·C₁₁ + V₇·C₁+ V₈·C₁₂)

Equation 7:

S₃= SC₁·(V₁·C₃+ V₂·C₁₅ + V₃·C₁₀ + V₄·C₉ + V₅·C₁₁ + V₆·C₇ + V₇·C₂ + V₈·C₁₂)

+ SC₂·(V₁·C₄+ V₂·C₁₆ + V₃·C₁₁ + V₄·C₁₀ + V₅·C₁₂ + V₆·C₃ + V₇·C₆ + V₈·C₁)

+ SC₃·(V₁·C₅+ V₂·C₁ + V₃·C₁₂ + V₄·C₁₁ + V₅·C₂ + V₆·C₁₃ + V₇·C₁₀ + V₈·C₉)

+ SC₄·(V₁·C₆+ V₂·C₂ + V₃·C₉ + V₄·C₁₂ + V₅·C₈ + V₆·C₁₄ + V₇·C₁₁ + V₈·C₁₀)

+ SC₅·(V₁·C₇+ V₂·C₃ + V₃·C₁₄ + V₄·C₁₃ + V₅·C₁₅ + V₆·C₁₁ + V₇·C₉ + V₈·C₁₆)

+ SC₆·(V₁·C₈+ V₂·C₄ + V₃·C₁₅ + V₄·C₁₄ + V₅·C₁₆ + V₆·C₁₂ + V₇·C₁₃ + V₈·C₂)

+ SC₇·(V₁·C₉+ V₂·C₅ + V₃·C₁₆ + V₄·C₁₅ + V₅·C₁ + V₆·C₈ + V₇·C₁₄ + V₈·C₁₃)

+ SC₈·(V₁·C₁₀+ V₂·C₆ + V₃·C₁₃ + V₄·C₁₆ + V₅·C₇ + V₆·C₄ + V₇·C₁₂ + V₈·C₁₄)

+ SC₉·(V₁·C₁₁+ V₂·C₇ + V₃·C₁ + V₄·C₄ + V₅·C₁₃ + V₆·C₁₀ + V₇·C₃ + V₈·C₅)

+ SC₁₀·(V₁·C₁₂+ V₂·C₈ + V₃·C₂ + V₄·C₁ + V₅·C₉ + V₆·C₁₆ + V₇·C₄ + V₈·C₃)

+ SC₁₁·(V₁·C₁₃+ V₂·C₉ + V₃·C₃ + V₄·C₂ + V₅·C₅ + V₆·C₁ + V₇·C₁₅+ V₈·C₄)

+ SC₁₂·(V₁·C₁₄+ V₂·C₁₀ + V₃·C₄ + V₄·C₃ + V₅·C₆ + V₆·C₂ + V₇·C₁+ V₈·C₈)

+ SC₁₃·(V₁·C₁₅+ V₂·C₁₁ + V₃·C₅+ V₄·C₈ + V₅·C₃ + V₆·C₉ + V₇·C₇+ V₈·C₆)

+ SC₁₄·(V₁·C₁₆+ V₂·C₁₂ + V₃·C₆+ V₄·C₅ + V₅·C₄ + V₆·C₁₅ + V₇·C₈+ V₈·C₇)

+ SC₁₅·(V₁·C₁+ V₂·C₁₃ + V₃·C₇+ V₄·C₆ + V₅·C₁₄ + V₆·C₅ + V₇·C₁₆+ V₈·C₁₁)

+ SC₁₆·(V₁·C₂+ V₂·C₁₄ + V₃·C₈+ V₄·C₇ + V₅·C₁₀ + V₆·C₆ + V₇·C₅+ V₈·C₁₅)

Equation 8:

S₄= SC₁·(V₁·C₄+ V₂·C₁₄ + V₃·C₆ + V₄·C₁₃ + V₅·C₁₆ + V₆·C₂ + V₇·C₉ + V₈·C₁₅)

+ SC₂·(V₁·C₅+ V₂·C₁₅ + V₃·C₇ + V₄·C₁₄ + V₅·C₁ + V₆·C₄ + V₇·C₃ + V₈·C₁₆)

+ SC₃·(V₁·C₆+ V₂·C₁₆ + V₃·C₈ + V₄·C₁₅ + V₅·C₇ + V₆·C₁₄ + V₇·C₇ + V₈·C₂)

+ SC₄·(V₁·C₇+ V₂·C₁ + V₃·C₅+ V₄·C₁₆ + V₅·C₂ + V₆·C₉ + V₇·C₈ + V₈·C₁₃)

+ SC₅·(V₁·C₈+ V₂·C₂ + V₃·C₁₀+ V₄·C₄ + V₅·C₉ + V₆·C₆ + V₇·C₆ + V₈·C₁₂)

+ SC₆·(V₁·C₉+ V₂·C₃ + V₃·C₁₁ + V₄·C₁+ V₅·C₅ + V₆·C₇ + V₇·C₁₀ + V₈·C₅)

+ SC₇·(V₁·C₁₀+ V₂·C₄ + V₃·C₁₂ + V₄·C₂ + V₅·C₆ + V₆·C₃ + V₇·C₁₁ + V₈·C₃)

+ SC₈·(V₁·C₁₁+ V₂·C₅ + V₃·C₉ + V₄·C₃ + V₅·C₁₂ + V₆·C₁₃ + V₇·C₁₆ + V₈·C₄)

+ SC₉·(V₁·C₁₂+ V₂·C₆ + V₃·C₁₄ + V₄·C₈ + V₅·C₄ + V₆·C₅ + V₇·C₁₃ + V₈·C₁)

+ SC₁₀·(V₁·C₁₃+ V₂·C₇ + V₃·C₁₅+ V₄·C₅ + V₅·C₁₄ + V₆·C₁₁ + V₇·C₁₄+ V₈·C₆)

+ SC₁₁·(V₁·C₁₄+ V₂·C₈ + V₃·C₁₆+ V₄·C₆ + V₅·C₁₀ + V₆·C₁₂ + V₇·C₁₂+ V₈·C₇)

+ SC₁₂·(V₁·C₁₅+ V₂·C₉ + V₃·C₁₃+ V₄·C₇ + V₅·C₁₁ + V₆·C₈ + V₇·C₅+ V₈·C₁₁)

+ SC₁₃·(V₁·C₁₆+ V₂·C₁₀ + V₃·C₁+ V₄·C₁₂ + V₅·C₈ + V₆·C₁₅ + V₇·C₄+ V₈·C₉)

+ SC₁₄·(V₁·C₁+ V₂·C₁₁ + V₃·C₂+ V₄·C₉ + V₅·C₃ + V₆·C₁₀ + V₇·C₁₅+ V₈·C₁₀)

+ SC₁₅·(V₁·C₂+ V₂·C₁₂ + V₃·C₃+ V₄·C₁₀ + V₅·C₁₃ + V₆·C₁₆ + V₇·C₁+ V₈·C₁₄)

+ SC₁₆·(V₁·C₃+V₂·C₁₃ + V₃·C₄+ V₄·C₁₁ + V₅·C₁₅ + V₆·C₁ + V₇·C₂+ V₈·C₈)

Reducing these Boolean equations using the fact that all C_ij’s are fixed at 1 or 0 and the Boolean relationships: X·1=X, X·0=0. As many of you saw at the outset, all terms containing cores equal to “0” vanish and all terms with cores equal to “1” remain without the core. S₁ becomes merely the start coordinates of cores that are “1”.

Equation 9:

S₁= SC₅ + SC₈ + SC₉+ SC₁₁ + SC₁₃ + SC₁₄ + SC₁₅+ SC₁₆

The other SET equations become:

Equation 10:

S₂= SC₁·(V₂ + V₃+ V₄ + V₇ + V₈)

+ SC₂·(V₃ + V₆ + V₇+ V₈)

+ SC₃·(V₃ + V₅ + V₇)

+ SC₄·(V₁+ V₃ + V₄ + V₆ + V₇)

+ SC₅·(V₄ + V₆)

+ SC₆·(V₂ + V₅ + V₈)

+ SC₇·(V₁+ V₄)

+ SC₈·(V₁+ V₇ + V₈)

+ SC₉·(V₂ + V₃+ V₄ + V₅ + V₆)

+ SC₁₀·(V₁+ V₂+ V₄ + V₅ + V₆ + V₈)

+ SC₁₁·(V₄ + V₅ + V₇+ V₈)

+ SC₁₂·(V₁+ V₂ + V₃ + V₄ + V₇+ V₈)

+ SC₁₃·(V₁+ V₃ + V₆)

+ SC₁₄·(V₁+ V₂ + V₅ + V₆ + V₇)

+ SC₁₅·(V₁+ V₂ + V₃ + V₅ + V₈)

+ SC₁₆·(V₂ + V₅ + V₆)

Equation 11:

S₃= SC₁·(V₂ + V₄ + V₅)

+ SC₂·(V₂ + V₃)

+ SC₃·(V₁+ V₄ + V₆ + V₈)

+ SC₄·(V₃+ V₅ + V₆ + V₇)

+ SC₅·(V₃+ V₄ + V₅ + V₆ + V₇ + V₈)

+ SC₆·(V₁+ V₃ + V₄ + V₅ + V₇)

+ SC₇·(V₁+ V₂ + V₃ + V₄ + V₆ + V₇+ V₈)

+ SC₈·(V₃ + V₄ + V₈)

+ SC₉·(V₁+ V₅ + V₈)

+ SC₁₀·(V₂+ V₅+ V₆)

+ SC₁₁·(V₁+ V₂ + V₅ + V₇)

+ SC₁₂·(V₁+ V₈)

+ SC₁₃·(V₁+ V₂ + V₃ + V₄ + V₆)

+ SC₁₄·(V₁+ V₄ + V₆ + V₇)

+ SC₁₅·(V₂+ V₅ + V₆ + V₇+ V₈)

+ SC₁₆·(V₂ + V₃+ V₈)

Equation 12:

S₄= SC₁·(V₂+ V₄+ V₅ + V₇ + V₈)

+ SC₂·(V₁+ V₂+ V₄+ V₈)

+ SC₃·(V₂+ V₃+ V₄+ V₆)

+ SC₄·(V₃+V₄+ V₆+ V₇+ V₈)

+ SC₅·(V₁+ V₅)

+ SC₆·(V₁+ V₃+ V₅+ V₈)

+ SC₇·(V₇)

+ SC₈·(V₁+ V₂+ V₃+ V₆+ V₇)

+ SC₉·(V₃+ V₄+ V₆+ V₇)

+ SC₁₀·(V₁+ V₃+ V₄+ V₅+ V₆ + V₇)

+ SC₁₁·(V₁+ V₂+ V₃)

+ SC₁₂·(V₁+ V₂+ V₃+ V₅+ V₆ + V₇+ V₈)

+ SC₁₃·(V₁+ V₅+ V₆+ V₈)

+ SC₁₄·(V₂+ V₄+ V₇)

+ SC₁₅·(V₅+ V₆+ V₈)

+ SC₁₆·(V₂+ V₄+ V₅+ V₈)

POOF! The CORE is gone! Only the logic circuits remain to output 110 (4-bit) words!!?? Where are those 110 words stored? IN THE LOGIC / CIRCUIT?

Logic equations 9 through 12 provide a view of the input seen by each of the four output devices in terms of each Start Coordinate and associated Read Vectors. Another view appears when we reduce equations 10, 11 and 12 by (a) expand, (b) rearrange and (c) reduce.

10a

S₂= V₂·SC₁ + V₃·SC₁+ V₄·SC₁ + V₇·SC₁ + V₈·SC₁

+ V₃·SC₂ + V₆·SC₂ + V₇·SC₂+ V₈·SC₂

+ V₃·SC₃ + V₅·SC₃ + V₇·SC₃

+ V₁·SC₄+ V₃·SC₄ + V₄·SC₄ + V₆·SC₄ + V₇·SC₄

+ V₄·SC₅ + V₆·SC₅

+ V₂·SC₆ + V₅·SC₆ + V₈·SC₆

+ V₁·SC₇+ V₄·SC₇

+ V₁·SC₈+ V₇·SC₈ + V₈·SC₈

+ V₂·SC₉ + V₃·SC₉+ V₄·SC₉ + V₅·SC₉ + V₆·SC₉

+ V₁·SC₁₀+ V₂·SC₁₀+ V₄·SC₁₀ + V₅·SC₁₀ + V₆·SC₁₀ + V₈·SC₁₀

+ V₄·SC₁₁ + V₅·SC₁₁ + V₇·SC₁₁+ V₈·SC₁₁

+ V₁·SC₁₂+ V₂·SC₁₂ + V₃·SC₁₂ + V₄·SC₁₂ + V₇·SC₁₂+ V₈·SC₁₂

+ V₁·SC₁₃+ V₃·SC₁₃ + V₆·SC₁₃

+ V₁·SC₁₄+ V₂·SC₁₄ + V₅·SC₁₄ + V₆·SC₁₄ + V₇·SC₁₄

+ V₁·SC₁₅+ V₂·SC₁₅ + V₃·SC₁₅ + V₅·SC₁₅ + V₈·SC₁₅

+ V₂·SC₁₆ + V₅·SC₁₆ + V₆·SC₁₆

10b

S₂= V₁·SC₄+ V₁·SC₇+ V₁·SC₈+ V₁·SC₁₀+ V₁·SC₁₂+ V₁·SC₁₃+ V₁·SC₁₄+ V₁·SC₁₅

+ V₂·SC₁+ V₂·SC₆+ V₂·SC₉+ V₂·SC₁₀+ V₂·SC₁₂ + V₂·SC₁₄+ V₂·SC₁₅+ V₂·SC₁₆

+ V₃·SC₁+ V₃·SC₂+ V₃·SC₃ + V₃·SC₄+ V₃·SC₉+ V₃·SC₁₂+ V₃·SC₁₃+ V₃·SC₁₅

+ V₄·SC₁+ V₄·SC₄+ V₄·SC₅+ V₄·SC₇+ V₄·SC₉+ V₄·SC₁₀+ V₄·SC₁₁+ V₄·SC₁₂

+ V₅·SC₃+ V₅·SC₆+ V₅·SC₉+ V₅·SC₁₀+ V₅·SC₁₁ + V₅·SC₁₄+ V₅·SC₁₅+ V₅·SC₁₆

+ V₆·SC₂+ V₆·SC₄+ V₆·SC₅+ V₆·SC₉+ V₆·SC₁₀ + V₆·SC₁₃+ V₆·SC₁₄+ V₆·SC₁₆

+ V₇·SC₁+ V₇·SC₂+ V₇·SC₃+ V₇·SC₄+ V₇·SC₈ + V₇·SC₁₁+ V₇·SC₁₂+ V₇·SC₁₄

+ V₈·SC₁+ V₈·SC₂+ V₈·SC₆+ V₈·SC₈+ V₈·SC₁₀+ V₈·SC₁₁+ V₈·SC₁₂+ V₈·SC₁₅

10c

S₂= V₁·(SC₄+ SC₇+ SC₈+ SC₁₀+ SC₁₂+ SC₁₃+ SC₁₄+ SC₁₅)

+ V₂·(SC₁+ SC₆+ SC₉+ SC₁₀+ SC₁₂ + SC₁₄+ SC₁₅+ SC₁₆)

+ V₃·(SC₁+ SC₂+ SC₃+ SC₄+ SC₉+ SC₁₂+ SC₁₃+ SC₁₅)

+ V₄·(SC₁+ SC₄+ SC₅+ SC₇+ SC₉+ SC₁₀+ SC₁₁+ SC₁₂)

+ V₅·(SC₃+ SC₆+ SC₉+ SC₁₀+ SC₁₁ + SC₁₄+ SC₁₅+ SC₁₆)

+ V₆·(SC₂+ SC₄+ SC₅+ SC₉+ SC₁₀ + SC₁₃+ SC₁₄ + SC₁₆)

+ V₇·(SC₁+ SC₂+ SC₃+ SC₄+ SC₈ + SC₁₁+ SC₁₂+ SC₁₄)

+ V₈·(SC₁+ SC₂+ SC₆+ SC₈+

11a

S₃= V₂·SC₁ + V₄·SC₁ + V₅·SC₁

+ V₂·SC₂ + V₃·SC₂

+ V₁·SC₃+ V₄·SC₃ + V₆·SC₃ + V₈·SC₃

+ V₃·SC₄+ V₅·SC₄ + V₆·SC₄ + V₇·SC₄

+ V₃·SC₅+ V₄·SC₅ + V₅·SC₅ + V₆·SC₅ + V₇·SC₅ + V₈·SC₅

+ V₁·SC₆+ V₃·SC₆ + V₄·SC₆ + V₅·SC₆ + V₇·SC₆)

+ V₁·SC₇+ V₂·SC₇ + V₃·SC₇ + V₄·SC₇ + V₆·SC₇ + V₇·SC₇+ V₈·SC₇

+ V₃·SC₈ + V₄·SC₈ + V₈·SC₈

+ V₁·SC₉+ V₅·SC₉ + V₈·SC₉

+ V₂·SC₁₀+ V₅·SC₁₀+ V₆·SC₁₀

+ V₁·SC₁₁+ V₂·SC₁₁ + V₅·SC₁₁ + V₇·SC₁₁

+ V₁·SC₁₂+ V₈·SC₁₂

+ V₁·SC₁₃+ V₂·SC₁₃ + V₃·SC₁₃ + V₄·SC₁₃ + V₆·SC₁₃

+ V₁·SC₁₄+ V₄·SC₁₄ + V₆·SC₁₄ + V₇·SC₁₄

+ V₂·SC₁₅+ V₅·SC₁₅ + V₆·SC₁₅ + V₇·SC₁₅+ V₈·SC₁₅

+ V₂·SC₁₆ + V₃·SC₁₆+ V₈·SC₁₆

11b

S₃= V₁·SC₃+ V₁·SC₆+ V₁·SC₇+ V₁·SC₉+ V₁·SC₁₁+ V₁·SC₁₂+ V₁·SC₁₃+ V₁·SC₁₄

+ V₂·SC₁+ V₂·SC₂+ V₂·SC₇+ V₂·SC₁₀+ V₂·SC₁₁ + V₂·SC₁₃+ V₂·SC₁₅+ V₂·SC₁₆

+ V₃·SC₂+ V₃·SC₄+ V₃·SC₅+ V₃·SC₆+ V₃·SC₇+ V₃·SC₈ + V₃·SC₁₃+ V₃·SC₁₆

+ V₄·SC₁+ V₄·SC₃+ V₄·SC₅+ V₄·SC₆+ V₄·SC₇+ V₄·SC₈+ V₄·SC₁₃+ V₄·SC₁₄

+ V₅·SC₁+ V₅·SC₄+ V₅·SC₅+ V₅·SC₆+ V₅·SC₉+ V₅·SC₁₀+ V₅·SC₁₁+ V₅·SC₁₅

+ V₆·SC₃+ V₆·SC₄ + V₆·SC₅+ V₆·SC₇+ V₆·SC₁₀+ V₆·SC₁₃+ V₆·SC₁₄+ V₆·SC₁₅

+ V₇·SC₄+ V₇·SC₅+ V₇·SC₆+ V₇·SC₇+ V₇·SC₁₁+ V₇·SC₁₄+ V₇·SC₁₅

+ V₈·SC₃+ V₈·SC₅+ V₈·SC₇+ V₈·SC₈+ V₈·SC₉+ V₈·SC₁₂+ V₈·SC₁₅+ V₈·SC₁₆

11c

S₃= V₁·(SC₃+ SC₆+ SC₇+ SC₉+ SC₁₁+ SC₁₂+ SC₁₃+ SC₁₄)

+ V₂·(SC₁+ SC₂+ SC₇+ SC₁₀+ SC₁₁ + SC₁₃+ SC₁₅+ SC₁₆)

+ V₃·(SC₂+ SC₄+ SC₅+ SC₆+ SC₇+ SC₈ + SC₁₃+ SC₁₆)

+ V₄·(SC₁+ SC₃+ SC₅+ SC₆+ SC₇+ SC₈+ SC₁₃+ SC₁₄ )

+ V₅·(SC₁+ SC₄+ SC₅+ SC₆+ SC₉+ SC₁₀+ SC₁₁+ SC₁₅)

+ V₆·(SC₃+ SC₄ + SC₅+ SC₇+ SC₁₀+ SC₁₃+ SC₁₄+ SC₁₅)

+ V₇·(SC₄+ SC₅+ SC₆+ SC₇+ SC₁₁+ SC₁₄+ SC₁₅ )

+ V₈·(SC₃+ SC₅+ SC₇+ SC₈+ SC₉+ SC₁₂+ SC₁₅+ SC₁₆)

12a

S₄= V₂·SC₁+ V₄·SC₁+ V₅·SC₁ + V₇·SC₁ + V₈·SC₁

+ V₁·SC₂+ V₂·SC₂+ V₄·SC₂+ V₈·SC₂

+ V₂·SC₃+ V₃·SC₃+ V₄·SC₃+ V₆·SC₃

+ V₃·SC₄+V₄·SC₄+ V₆·SC₄+ V₇·SC₄+ V₈·SC₄

+ V₁·SC₅+ V₅·SC₅

+ V₁·SC₆+ V₃·SC₆+ V₅·SC₆+ V₈·SC₆

+ V₇·SC₇

+ V₁·SC₈+ V₂·SC₈+ V₃·SC₈+ V₆·SC₈+ V₇·SC₈

+ V₃·SC₉+ V₄·SC₉+ V₆·SC₉+ V₇·SC₉

+ V₁·SC₁₀+ V₃·SC₁₀+ V₄·SC₁₀+ V₅·SC₁₀+ V₆·SC₁₀ + V₇·SC₁₀

+ V₁·SC₁₁+ V₂·SC₁₁+ V₃·SC₁₁

+ V₁·SC₁₂+ V₂·SC₁₂+ V₃·SC₁₂+ V₅·SC₁₂+ V₆·SC₁₂ + V₇·SC₁₂+ V₈·SC₁₂

+ V₁·SC₁₃+ V₅·SC₁₃+ V₆·SC₁₃+ V₈·SC₁₃

+ V₂·SC₁₄+ V₄·SC₁₄+ V₇·SC₁₄

+ V₅·SC₁₅+ V₆·SC₁₅+ V₈·SC₁₅

+ V₂·SC₁₆+ V₄·SC₁₆+ V₅·SC₁₆+ V₈·SC₁₆

12b

S₄= V₁·SC₂+ V₁·SC₅+ V₁·SC₆+ V₁·SC₈+ V₁·SC₁₀+ V₁·SC₁₁+ V₁·SC₁₂+ V₁·SC₁₃

+ V₂·SC₁+ V₂·SC₂+ V₂·SC₃+ V₂·SC₈+ V₂·SC₁₁+ V₂·SC₁₂+ V₂·SC₁₄+ V₂·SC₁₆

+ V₃·SC₃+ V₃·SC₆+ V₃·SC₈+ V₃·SC₉+ V₃·SC₁₀+ V₃·SC₁₁+ V₃·SC₁₂

+ V₄·SC₁+ V₄·SC₂+ V₄·SC₃+ V₄·SC₄+ V₄·SC₉+ V₄·SC₁₀+ V₄·SC₁₄+ V₄·SC₁₆

+ V₅·SC₁+ V₅·SC₅+ V₅·SC₆+ V₅·SC₁₀+ V₅·SC₁₂+ V₅·SC₁₃+ V₅·SC₁₅+ V₅·SC₁₆

+ V₆·SC₃+ V₆·SC₈+ V₆·SC₉+ V₆·SC₁₀+ V₆·SC₁₂+ V₆·SC₁₃+ V₆·SC₁₅

+ V₇·SC₁+ V₇·SC₄+ V₇·SC₇+ V₇·SC₈+ V₇·SC₉+ V₇·SC₁₀+ V₇·SC₁₂+ V₇·SC₁₄

+ V₈·SC₁+ V₈·SC₂+ V₈·SC₄+ V₈·SC₆+ V₈·SC₁₂+ V₈·SC₁₃+ V₈·SC₁₅+ V₈·SC₁₆

12c

S₄= V₁·(SC₂+ SC₅+ SC₆+ SC₈+ SC₁₀+ SC₁₁+ SC₁₂+ SC₁₃)

+ V₂·(SC₁+ SC₂+ SC₃+ SC₈+ SC₁₁+ SC₁₂+ SC₁₄+ SC₁₆)

+ V₃·(SC₃+ SC₆+ SC₈+ SC₉+ SC₁₀+ SC₁₁+ SC₁₂)

+ V₄·(SC₁+ SC₂+ SC₃+ SC₄+ SC₉+ SC₁₀+ SC₁₄+ SC₁₆)

+ V₅·(SC₁+ SC₅+ SC₆+ SC₁₀+ SC₁₂+ SC₁₃+ SC₁₅+ SC₁₆)

+ V₆·(SC₃+ SC₈+ SC₉+ SC₁₀+ SC₁₂+ SC₁₃+ SC₁₅)

+ V₇·(SC₁+ SC₄+ SC₇+ SC₈+ SC₉+ SC₁₀+ SC₁₂+ SC₁₄)

+ V₈·(SC₁+ SC₂+ SC₄+ SC₆+ SC₁₂+ SC₁₃+ SC₁₅+ SC₁₆)

These logic equations can be burned into circuits which will produce, and output, the 4-bit words called out in tables 1 though 8. One way of looking at this is that the data (110: 4-bit words) is stored in the SET (set output to “1”) logic circuits. However when we move to larger words, stored using more sophisticated storage techniques, in as many dimensions as we choose, this picture of the data stored in the logic breaks down. Consider information stored in the human brain. We have 10¹⁰ neurons (delay elements). We store in excess of 10⁶⁰ bits of information in 30 years of living according to Von Neuman (reference).

Another way of looking says that the data is in “Information Space” and the logic circuits taken together is the real world transform (T prime of equation 3 chapter 1 of The Physics of Thought - reference) containing the addresses of the data. To see how this can be done, consider the following expansion direction.

The size of the address: 4 bits for the Start Coordinate and 3 bits for the Read Vector. The total is a 7-bit address of a 4-bit word. If the word size is increased we find that the address size does not increase at the same rate.

Suppose we now move to a cube (x,y,z) 256 bits on an edge. AND suppose we can find a distribution of “1”s and “0”s such that EVERY 256-bit word can be found in every read direction as demonstrated with the 110 4-bit words discussed above. Considering addressing schemes of the type we have been exploring, we find that it requires 8 bits to specify a “Start Coordinate” in each direction in our cube: 2⁸=256. Therefore 24 (3 axes x 8) bits are used in the “Start Coordinate”.