ICM

T h e I N F I N I T E C A P A C I T Y M E M O R Y

Kenneth N. Brown

Advanced Research Consultants, Inc

Abstract:

This paper opens the door to new ways of storing extremely large amounts of information without using traditional storage media. I show in detail how to read 110 4-bit words out of a 4 by 4 core. The reduced logic equations, developed to output any of the 110 4-bit words, show the core to be virtual. i.e. The core vanishes from the equations leaving only the logic equations/circuits accepting the addresses and outputting the data.

Only the logic remains!!?? Is this a clue to how our memory works? Is this a clue to how DNA memory works? Can we duplicate such memory schemas by expanding this 4 by 4 scheme to usable computer word sizes? Is it possible to store astronomical amounts of data by merely creating logic equations to output the data?

The remainder of the paper explores a range of implementation methods and associated memory sizes. I begin by showing tag (linked) storage technique to store "unlimited" amounts of data. The term "unlimited" is quantified by "unique addresses" in powers of ten. I demonstrate the exponential increase in storage capacity as a result each of the following: (1) Increasing the dimensions of the virtual core; (2) Increasing the word size; (3) changing read direction every "n" bits during the read out of a word. The largest capacity discussed, in terms of unique addresses, is greater than 10 to the 75th power.

Omitted from this paper are implementation software analysis, design, programming and programs.

In the conventional digital storage techniques, we store strings of 1s and 0s. Figure 1 below represents four 4-bit words stored in an old fashioned 4 X 4 magnetic core array: 0000, 1001, 1010, and 1111. A core element that is “turned on” is shown containing a 1. A “turned off” core element is 0. We use the hexadecimal (base 16) notation to simplify the description of binary numbers. Therefore those four 4 bit words are 0₁₆ = 0000, 9₁₆ = 1001, A₁₆ = 1010 and F₁₆ = 1111 represented simply by 0, 9, A and F.

Figure 1

These four 4 bit words (W) are output into a readout register (R). Figure 2 is a diagram of the word selection and output.

Figure 2

The four output register bi-stable devices are set(to “1”) by the following logic equations:

1. R1 = C11·W1 + C21·W2 + C31·W3 + C41·W4

2. R2 = C12·W1 + C22·W2 + C32·W3 + C42·W4

3. R3 = C13·W1 + C23·W2 + C33·W3 + C43·W4

4. R4 = C14·W1 + C24·W2 + C34·W3 + C44·W4

In a move away from this conventional model of computer storage, I propose to read the core of figure 1 by defining a start coordinate and a direction to read a 4-bit word. The model of figure 3 shows the scan pattern for the +X direction.

Figure 3

When we scan our 4 x 4 core with various start coordinates (SC), we can read out all sixteen 4-bit words:

Table 1

NR. Read	Address		Sequence of cores read
NR. Read	SC	Dir	Sequence of cores read	Binary	Hex
0	1	+X	1,2,3,4	0000	0
1	2	+X	2,3,4,5	0001	1
2	3	+X	3,4,5,6	0010	2
3	6	+X	6,7,8,9	0011	3

4	4	+X	4,5,6,7	0100	4
5	10	+X	10,11,12,13	0101	5
6	7	+X	7,8,9,10	0110	6
7	12	+X	12,13,14,15	0111	7
8	16	+X	16,1,2,3	1000	8
9	5	+X	5,6,7,8	1001	9
10	9	+X	9,10,11,12	1010	A
11	11	+X	11,12,13,14	1011	B
12	15	+X	15,16,1,2	1100	C
13	8	+X	8,9,10,11	1101	D

14,15,16,1

1110

E

13,14,15,16

1111

Address

A

D

E

F